Thermal shutdown (“TSD”) circuits are used to shut down a particular module within an integrated circuit (“IC”) when the temperature of that module exceeds a certain temperature. One of the ways such circuits are implemented is as follows. A reference circuit generates current that is proportional to absolute temperature (“IPTAT”). This IPTAT current is fed into a thermal sensor, which is typically a bipolar transistor and a resistor. An example 10 of such a prior art circuit is shown in FIG. 1. The Reference circuit 11 is a well-known circuit for generating a PTAT current via the difference between current densities through transistors Q1 and Q2, which have a ratio of emitter areas of 1:N. PFET transistor devices MP1 and MP2 are configured as a current mirror, and mirror the PTAT current to PFET transistor device MP3 in the Thermal Sensor circuit 12. The PTAT current is conducted through resistor R2 in Thermal Sensor circuit 12, which establishes a voltage Va at the base of bipolar transistor Q3. FIG. 2 is a graph of voltage versus temperature showing plots for Va versus temperature and of the base-emitter voltage Vbe of transistor Q3 versus temperature. When Va exceeds the Vbe, transistor Q3 turns on, overcoming the pull-up function of current source M and pulling the normally high level TSD OUT signal down, thus signaling thermal shutdown.
Some modules that are provided with a TSD circuit have an FET that is designed for relatively low ON resistance, which requires that the size of the FET be relatively large. The drains of such FET devices are typically connected to an external pin of the IC. During normal operation, the drain is tied to a power supply through a load, which has a selected resistance. In such configurations, a fault condition can occur in which the drain gets short circuited to the power supply without the load. If the FET is in the ON state when this type of fault condition occurs, a large amount of current flows through the FET, limited only by its size. For this reason, a current limit circuit is frequently implemented to deal with this situation. The current limit circuit uses a sense FET the size of which is a fraction of that of the FET being protected. Therefore, the current through the sense FET is likewise a fraction of that through the FET being protected. When the current through the sense FET exceeds a set value, the current limit circuit operates on the gate voltage of the FET being protected to limit the current through it.
In cases where the current limit value is set high, at the time that this kind of fault condition occurs, a large amount of power is instantaneously dissipated in the FET being protected. This causes highly localized heating. The heat from the center of the FET radiates to the TSD circuit, and, as described above, when the temperature of the TSD circuit reaches its trip point, the TSD OUT signal changes state, causing shut-down of the module. If the temperature of the TSD circuit is relatively low when the fault occurs, it takes relatively longer for it to reach its trip point, and in the meantime, the highly localized heating in the FET being protected could damage it.
It would be desirable to have a TSD circuit that is less susceptible to this kind of failure in its protective function.